Latch-up is a condition in which a circuit draws uncontrolled amounts of current, and certain voltages are forced, or “latched-up,” to some undesirable and uncontrollable level that violates the operating conditions of the circuit. Latch-up conditions are most often caused by crosstalk between devices in an integrated circuit.
In an integrated circuit (IC) having multiple devices monolithically built on the same substrate, unintended parasitic devices such as transistors, diodes, or resistors may cause undesirable crosstalk between other devices. Undesirable crosstalk between devices may exist in bipolar integrated circuits, as well as field effect transistors such as a metal-oxide-semiconductor field effect transistor (MOSFET).
By way of example, in a complimentary metal-oxide-semiconductor (CMOS) based integrated circuit, an n-well, a p-substrate, and another n-doped region may form a parasitic NPN transistor. The parasitic NPN transistor may be turned on when one of the PN junctions in the transistor is forward-biased. This may undesirably cause latch-up of another device on the integrated circuit and, in some cases, even permanently damage the integrated circuit.
One conventional method of preventing latch-up involves surrounding the NMOS and PMOS transistors (both input/output (I/O) and logic) with a guard ring. Such guard rings may be able to collect parasitic NPN and PNP currents locally and prevent unintentional turn-on of adjacent devices.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.